Solid CVD Silicon Carbide Focus Ring

Why Go Solid SiC Instead of Silicon or Coated Graphite?

If you’ve run a conventional silicon focus ring for a few thousand wafers, you’ve probably seen the edge rate drift – that’s the silicon eroding. Over time, the ring loses material, the plasma boundary shifts, and your etch profile changes. You can compensate by tweaking bias power or pressure, but eventually you’re chasing a moving target.

Solid CVD SiC solves that. It erodes at a fraction of the rate – typically 10-20× slower than high-purity silicon in aggressive Bosch or oxide etch processes. And because it’s a single-piece material (not a coating on graphite), there’s no risk of delamination or micro-cracking after repeated thermal cycles. You get a stable geometry that holds its dimensions for months, not weeks.

That stability translates directly into:

Fewer process drifts – you can keep your recipe parameters unchanged for longer.

Lower particle counts – no coating spallation, no flaking.

Less frequent chamber opens – maintenance intervals stretch out, which boosts tool uptime.

Consistent CD and profile at the wafer edge – especially critical for 3D NAND, DRAM, and advanced logic.

What We Build into Every Ring?

Purity you can trust. Our CVD process produces β-SiC with total metallic impurities below 0.1 ppm – that’s 99.99999% purity on a good day. For sensitive layers like gate oxide or high-k dielectrics, that level of cleanliness matters.

Plasma resistance that holds up. Whether you’re running SF₆/O₂ for silicon deep-etch, C₄F₈/Ar for oxide, or Cl₂/BCl₃ for metal and compound semiconductors, the SiC surface stays intact. We’ve seen rings survive over 50,000 RF hours in production without visible erosion.

Thermal conductivity that evens out hot spots. With >150 W/m·K, solid SiC spreads heat far better than quartz or alumina. That means the ring stays cool under high-power plasma, and thermal expansion remains uniform – so the gap between ring and wafer doesn’t change as the chamber warms up.

A monolithic structure with no weak points. Coated graphite can be great for some applications, but when you need absolute reliability over extreme temperature swings, bulk CVD SiC is the safer bet. No interface, no CTE mismatch, no hidden cracks.

Machining precision down to microns. We CNC-grind each ring to fit OEM pocket dimensions – typical tolerances are ±0.02 mm on OD/ID, with flatness better than 10 µm. If you need a special chamfer, a stepped profile, or a custom thickness, we can adapt from your drawing.

How We Make Them – From CVD to Your Chamber

CVD growth – We deposit SiC on a sacrificial substrate, then separate the free-standing material. The process runs under tightly controlled temperature and gas ratios to achieve the right stoichiometry and grain structure.

Annealing – Relieves any residual stress, so the ring won’t warp during fast temperature ramps in the etcher.

Diamond grinding – We use multi-axis CNC machines with diamond wheels to cut the ring to final dimensions.

Lapping and polishing – The surface is refined to Ra < 0.2 µm, which reduces particle adhesion and improves contact with the chuck.

Cleaning – Ultrasonic bath with deionised water and mild detergent, followed by IPA rinsing and nitrogen drying.

Inspection – Every ring goes through CMM, roughness profiling, and 100% visual inspection under bright light.

Packaging – Single-layer cleanroom bagging, then vacuum-sealed outer packaging, ready for fab intake.

Quality Checks – We Don’t Skip Any

Each shipment includes a material test report (with GDMS data), a dimensional inspection sheet, a surface roughness record, and a certificate of cleanliness (particle count per cm²). We also retain samples from each batch for longer-term reliability tracking.

Why Fabs Choose Semixlab?

We’re a team that speaks etch – not just sales, but process engineers who have worked inside fabs. We know that a focus ring is not a commodity; it’s a part that directly affects your yield. We keep our lead times short (2-3 weeks for standard sizes), we communicate clearly about shipping and customs, and we stand behind every ring with full traceability. If you need a modification – say, a different edge radius or a special through-hole for gas flow – we can usually accommodate it without a long development cycle.

Quick Specs – What You Get

Where These Rings Are Used？

You’ll find our solid SiC focus rings in:

High-aspect-ratio (HAR) etching for 3D NAND and DRAM – where the aspect ratio pushes 100:1, and edge uniformity is make-or-break.

Logic manufacturing from 28 nm down to 3 nm – especially for gate and spacer etching.

SiC power device fabrication – because the ring itself is SiC, it doesn’t introduce any foreign metal contamination.

GaN HEMT processing – where plasma stability and low defect density are paramount.

MEMS and deep-silicon etching (Bosch process) – the ring handles the alternating SF₆ and C₄F₈ cycles without degradation.

Advanced packaging – e.g., TSV etch for 2.5D/3D integration.

We make rings compatible with Lam Research, Applied Materials, TEL, and other major etch platforms – and we can match not only the dimensions but also the dielectric properties (we can adjust resistivity if needed for RF coupling).